Field Programmable Gate Arrays (“FPGAs”) are popular devices for implementing electronic circuits. A basic FPGA contains Configurable Logic Blocks (“CLBs”), routing matrices and input/output (“I/O”) blocks. The combination of these provides flexibility and enables the configuration of almost any digital electronic circuit. The desired circuit can be implemented by configuring the CLBs using a software tool.
The interconnect architecture plays an important role in facilitating the configuration of the FPGAs. The interconnect architecture is required to provide maximum utilization of the logic resources available on chip, minimize latency, be simple to configure and occupy the smallest possible area on the chip.
Tiled interconnect architectures are popular because of their simplicity and reusability.
FIG. 1 shows the schematic diagram of a basic “quad line” tile 100 used to construct the interconnect architecture. The basic cell consist of configurable logic blocks 101, a band of routing segments 102 and vias 103, 104. The band of routing segments 102 comprises a plurality of interconnect segments, each of which connects two CLBs through via 103. The band of routing segments propagates through bent section 105 and through cross over layer 106 for connecting the first and the last interconnect segments through via 104.
FIG. 2 shows an interconnect architecture constructed by replicating the basic cell of FIG. 1. The interconnect segment starts and ends at an interface 201. As shown, for a “quad line” architecture, an interconnect segment traverses four tiles before terminating at another interface matrix 201. The line segment has bent sections 202 in the first three tiles and another fragment 203 in the fourth tile where the segment terminates. While fabricating a segment, the bent sections 202 are placed on a metal layer different from the metal layers for fragments 203. Vias link the fragments 203 and interconnect segments 204.
A similar type of interconnect architecture is described in U.S. Pat. No. 6,204,690. This patent uses a combination of single-length interconnect lines connecting to adjacent tiles, and intermediate-length interconnect lines connecting to tiles separated further apart. This arrangement results in an interconnect hierarchy that allows any logic block to be connected to any other logic block. This also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles.
U.S. Pat. No. 5,760,604, provides an interconnect architecture that uses logic-unit output lines, of more than one length and provides extension lines to increase the reach of a logic unit output line.
All the patents mentioned above describe symmetric tile architectures for a programmable device requiring a physical staggering of routing lines. A line/group of lines are staggered in a tile to maintain tile symmetry. These tiles when replicated and placed next to each other, generate a routing channel with multiple length lines in the channel.
The interconnect architecture as described in above referred patents and any channel generation by tile replication in the manner described suffers following drawbacks.
A signal propagating between two ports has to pass through a series of vias and interconnect layers resulting in increased signal delays.
Interconnect layers are extensively bent along the signal path leading to electro-migration issues.
Introduction of extra interconnect layers in the physical layout restricts other connectivity.